? semiconductor components industries, llc, 2011 may, 2011 ? rev. 7 1 publication order number: mc74vhct50a/d mc74vhct50a noninverting buffer / cmos logic level shifter with lsttl ? compatible inputs the mc74vhct50a is a hex noninverting buffer fabricated with silicon gate cmos technology. it achieves high speed operation similar to equivalent bipolar schottky ttl while maintaining cmos low power dissipation. the internal circuit is composed of three stages, including a buf fered output which provides high noise immunity and stable output. the device input is compatible with ttl ? type input thresholds and the output has a full 5 v cmos level output swing. the input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic ? level translator from 3.0 v cmos logic to 5.0 v cmos logic or from 1.8 v cmos logic to 3.0 v cmos logic while operating at the high ? voltage power supply. the mc74vhct50a input structure provides protection when voltages up to 7 v are applied, regardless of the supply voltage. this allows the mc74vhct50a to be used to interface 5 v circuits to 3 v circuits. the output structures also provide protection when v cc = 0 v. these input and output structures help prevent device destruction caused by supply voltage ? input/output voltage mismatch, battery backup, hot insertion, etc. ? high speed: t pd = 3.5 ns (typ) at v cc = 5 v ? low power dissipation: i cc = 2 a (max) at t a = 25 c ? ttl ? compatible inputs: v il = 0.8 v; v ih = 2.0 v ? cmos ? compatible outputs: v oh > 0.8 v cc ; v ol < 0.1 v cc @load ? power down protection provided on inputs and outputs ? these devices are pb ? free and are rohs compliant logic diagram y1 a1 a2 a3 a4 a5 a6 y2 y3 y4 y5 y6 1 3 5 9 11 13 2 4 6 8 10 12 y = a a1 y1 1 a2 y2 1 a3 y3 1 a4 y4 1 a5 y5 1 a6 y6 1 logic symbol 14 ? lead soic d suffix case 751a 14 ? lead tssop dt suffix case 948g pin connection and marking diagram (top view) 13 14 12 11 10 9 8 2 1 34567 v cc a6 y6 a5 y5 a4 y4 a1 y1 a2 y2 a3 y3 gnd 14 ? lead soeiaj m suffix case 965 function table l h a input y output l h for detailed package marking information, see the marking diagram section on page 4 of this data sheet. http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ordering information
mc74vhct50a http://onsemi.com 2 maximum ratings symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v in dc input voltage 0.5 v i 7.0 v v out dc output voltage output in high or low state (note 1) 0.5 v o 7.0 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output source/sink current 25 ma i cc dc supply current per supply pin 50 ma i gnd dc ground current per ground pin 50 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance soic tssop 125 170 c/w p d power dissipation in still air soic tssop 500 450 mw v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) > 2000 > 200 2000 v i latch ? up latch ? up performance above v cc and below gnd at 85 c (note 5) 300 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. i o absolute maximum rating must be observed. 2. tested to eia/jesd22 ? a114 ? a. 3. tested to eia/jesd22 ? a115 ? a. 4. tested to jesd22 ? c101 ? a. 5. tested to eia/jesd78. recommended operating conditions characteristics symbol min max unit dc supply voltage v cc 2.0 5.5 v dc input voltage v in 0.0 5.5 v dc output voltage v cc = 0 high or low state v out 0.0 0.0 5.5 v cc v operating temperature range t a ? 55 +125 c input rise and fall time v cc = 3.3 v 0.3 v v cc = 5.0 v 0.5 v t r , t f 0 0 100 20 ns/v 3.0v gnd 50% 50% v cc a y t phl t plh *includes all probe and jig capacitance c l * test point device under test output figure 1. switching waveforms figure 2. test circuit v oh v ol
mc74vhct50a http://onsemi.com 3 dc electrical characteristics v cc t a = 25 c t a 85 c t a 125 c symbol parameter test conditions (v) min typ max min max min max unit v ih minimum high ? level input voltage 3.0 4.5 5.5 1.2 2.0 2.0 1.2 2.0 2.0 1.2 2.0 2.0 v v il maximum low ? level input voltage 3.0 4.5 5.5 0.53 0.8 0.8 0.53 0.8 0.8 0.53 0.8 0.8 v v oh minimum high ? level output voltage v in = v ih or v il v in = v ih or v il i oh = ? 50 a 3.0 4.5 2.9 4.4 3.0 4.5 2.9 4.4 2.9 4.4 v v in = v ih or v il i oh = ? 4 ma i oh = ? 8 ma 3.0 4.5 2.58 3.94 2.48 3.80 2.34 3.66 v v ol maximum low ? level output voltage v in = v ih or v il v in = v ih or v il i ol = 50 a 3.0 4.5 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il i oh = ? 4 ma i ol = 8 ma 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 v i in maximum input leakage current v in = 5.5 v or gnd 0 to 5.5 0.1 1.0 1.0 a i cc maximum quiescent supply current v in = v cc or gnd 5.5 2.0 20 40 a i cct quiescent supply current input: v in = 3.4 v 5.5 1.35 1.50 1.65 ma i off output leakage current v out = 5.5 v 0.0 0.5 5.0 10 a ????????????????????????????????? ????????????????????????????????? ac electrical characteristics (c load = 50 pf, input t r = t f = 3.0ns) symbol parameter test conditions t a = 25 c t a 85 c t a 125 c unit min typ max min max min max t plh , t phl maximum propogation delay, input a to y v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf 5.5 8.0 7.9 11.4 1.0 1.0 9.5 13.0 ns v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf 6.2 7.0 7.5 8.5 8.5 9.5 9.5 10.5 c in maximum input capacitance 5 10 10 10 pf c pd power dissipation capacitance (note 6) typical @ 25 c, v cc = 5.0 v pf 15 6. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc . c pd is used to determine the no ? load dynamic power consumption; p d = c pd v cc 2 f in + i cc v cc . noise characteristics (input t r = t f = 3.0ns, c l = 50pf, v cc = 5.0v) symbol characteristic t a = 25 c unit typ max v olp quiet output maximum dynamic v ol 0.8 1.0 v v olv quiet output minimum dynamic v ol ? 0.8 ? 1.0 v v ihd minimum high level dynamic input voltage 2.0 v v ild maximum low level dynamic input voltage 0.8 v
mc74vhct50a http://onsemi.com 4 ordering information device package shipping ? mc74vhct50adg soic ? 14 (pb ? free) 55 units / rail mc74vhct50adr2g soic ? 14 (pb ? free) 2500 / tape & reel mc74vhct50adtg tssop ? 14 (pb ? free) 96 units / rail mc74vhct50adtr2g tssop ? 14 (pb ? free) 2500 / tape & reel mc74vhct50amg soeiaj (pb ? free) 50 units / rail mc74vhct50amelg soeiaj (pb ? free) 2000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. marking diagrams (top view) 14 ? lead soic d suffix case 751a 14 ? lead tssop dt suffix case 948g 13 14 12 11 10 9 8 2 1 34567 13 14 12 11 10 9 8 2 1 34567 14 ? lead soeiaj m suffix case 965 13 14 12 11 10 9 8 2 1 34567 vhct50ag awlyww* *see applications note #and8004/d for date code and traceability information. 74vhct50a alywg* vhct 50a alyw a = assembly location wl, l = wafer lot y = year ww, w = work week g or = pb ? free package
mc74vhct50a http://onsemi.com 5 package dimensions soic ? 14 d suffix case 751a ? 03 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 7.04 14x 0.58 14x 1.52 1.27 dimensions: millimeters 1 pitch soldering footprint 7x
mc74vhct50a http://onsemi.com 6 package dimensions tssop ? 14 case 948g ? 01 issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint
mc74vhct50a http://onsemi.com 7 package dimensions soeiaj ? 14 case 965 ? 01 issue b h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.004 0.008 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. mc74vhct50a/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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